| PART |
Description |
Maker |
| 74VHC11207 74VHC112MTCNL 74VHC112 |
Dual J-K Flip-Flops with Preset and Clear
Dual J-K Flip-Flops with Preset and Clear AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
Fairchild Semiconductor, Corp.
|
| HD74LS107A HD74LS107AFP HD74LS107AP HD74LS107ARP |
Dual J-K Flip-Flops with Clear
Dual J-K Negative-edge-triggered Flip-Flops(with Clear)
FLIP-FLOP|DUAL|J/K TYPE|LS-TTL|SOP|14PIN|PLASTIC
FLIP-FLOP|DUAL|J/K TYPE|LS-TTL|DIP|14PIN|PLASTIC
|
HITACHI[Hitachi Semiconductor]
|
| HCTS109HMSR HCTS109KMSR HCTS109K HCTS109D HCTS109D |
Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 辐射加固双JK触发器拖
Radiation Hardened Dual JK Flip Flop
From old datasheet system
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| HD74LS73A HD74LS73AP HD74LS73ARPEL |
Dual J-K Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| HD74HC113 |
Dual J-K Flip-Flops (with Preset)
|
HITACHI[Hitachi Semiconductor]
|
| MM74C73 MM74C73N MM74C76M MM74C76N |
Dual J-K Flip-Flops with Clear and Preset
|
FAIRCHILD[Fairchild Semiconductor]
|
| MM74C7304 |
Dual J-K Flip-Flops with Clear and Preset
|
Fairchild Semiconductor
|
| HCF4518 HCF4518B HCF4518BC1 HCF4518BEY HCF4518BF H |
Dual Up-Counters(???璁℃???
DUAL UP-COUNTERS 双向上计数器
Replaced by SN54S74 : Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-CDIP -55 to 125
Dual Up-Counters(双加计数
|
STMicroelectronics N.V.
意法半导
ST Microelectronics
SGS Thomson Microelectronics
|
| HD74LV74A |
Dual D-type Flip-Flops with Preset and Clear
|
Hitachi Semiconductor
|
| HD74LV74A HD74LV74AFPEL HD74LV74ARPEL HD74LV74ATEL |
Dual D-type Flip Flops with Preset and Clear
|
Renesas Electronics Corporation
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
